Intel® x86 Instruction Set Reference
Volume 1: Legacy Architecture (Up to 80486 DX4)

Document Number: X86-LEG-486-001
Revision Date: May 2025

This document provides a reference for the x86 instruction set supported by Intel processors from the 8086 through the 80486 DX4. It is intended for software developers targeting legacy systems.

1.0 8086/8088 Instructions (1978–1979)

The foundational instruction set for the x86 architecture, comprising core operations for data transfer, arithmetic, logic, and control flow.

Data Transfer
  • MOV: Copy data between registers/memory
  • PUSH/POP: Manage stack operations
  • XCHG: Swap register/memory contents
  • XLAT: Table-based byte translation
Arithmetic/Logic
  • ADD/SUB: Integer addition/subtraction
  • MUL/DIV: Unsigned multiplication/division
  • AND/OR/XOR: Bitwise operations
  • INC/DEC: Increment/decrement
Control Flow
  • JMP: Unconditional jump
  • Jcc: Conditional jumps (JE, JNE, etc.)
  • CALL/RET: Subroutine management
  • LOOP: Iteration control
String Operations
  • MOVSB/MOVSW: Block memory transfers
  • CMPSB/CMPSW: String comparisons
  • SCASB/SCASW: String scanning

2.0 80186/80188 Additions (1982)

Enhanced instructions for stack management and I/O operations, primarily for embedded applications.

System-Level Features
  • ENTER/LEAVE: Streamlined stack frame setup/teardown
  • BOUND: Array index bounds checking
  • PUSHA/POPA: Save/restore all general registers
I/O Enhancements
  • INSB/INSW: Block input from ports
  • OUTSB/OUTSW: Block output to ports
Immediate Operations
  • IMUL immediate: Signed multiplication with constants
  • Shift/Rotate immediate: Multi-bit shifts in single instruction

3.0 80286 Extensions (1982)

Introduced protected mode instructions for multitasking and memory protection.

Protected Mode Management
  • LGDT/LIDT: Load global/interrupt descriptor tables
  • LMSW: Set machine status word
  • CLTS: Clear task-switched flag
Privilege Control
  • ARPL: Adjust segment selector privilege level
  • VERR/VERW: Validate segment read/write access
Descriptor Access
  • LAR: Load access rights byte
  • LSL: Load segment limit

4.0 80386 Innovations (1985)

Expanded the ISA with 32-bit operations and advanced system control features.

32-Bit Operations
  • MOVSD: 32-bit string moves
  • PUSHAD/POPAD: 32-bit register stack management
  • IRETD: 32-bit interrupt returns
Bit Manipulation
  • BT/BTS/BTR/BTC: Bit test/modify operations
  • BSF/BSR: Bit scan forward/reverse
Addressing Modes
  • MOVZX/MOVSX: Zero/sign extension moves
  • LEA: Effective address calculation
System Control
  • MOV to/from CR/DR: Access control/debug registers

5.0 80486 Enhancements (1989–1994)

Optimized instructions for atomic operations and cache management.

Atomic Operations
  • CMPXCHG: Compare-and-swap primitive
  • XADD: Exchange-and-add
Data Manipulation
  • BSWAP: Endianness conversion
Cache Control
  • INVD: Invalidate cache
  • WBINVD: Write-back and invalidate
  • INVLPG: TLB entry invalidation

6.0 Compatibility Notes

Late 80486 models implemented CPUID through microcode updates, enabling software detection of processor capabilities via EFLAGS bit 21 manipulation. This instruction is officially a Pentium feature but is noted here for completeness.